This invention relates to the structure of digital circuits which add binary data bits; and more particularly, it relates to the structure of such adder circuits which operate a high speed.
In the prior art, digital adder circuits have been widely used. For example, they are used in the arithmetic units of general purpose digital computers, and they are also used in special purpose arithmetic modules such as a multiplier. In many of these applications, the speed at which the adder circuit operates is of critical importance.
Conventionally, digital adder circuits have been structured entirely of digital logic gates such as AND gates, NOR gates, EXCLUSIVE-OR gates, etc. One such adder circuit, for example, is the SN54HC283 which is sold by Texas Instruments. A logic diagram of that adder circuit is disclosed at page 2-369 of the "High-Speed CMOS Logic Data Book" from Texas Instruments, copyrighted 1987.
A problem, however, with an adder that is implemented entirely of logic gates is that the signal path from the carry-in terminal for the least significant data bits, to the carry-out terminal from the most significant data bits, goes through several logic gates in a series. Each logic gate imposes a certain time delay on the signal path, and thus the speed for generating the carry-out signal from the most significant data bits is limited by the serial gating.
Another structure in the prior art for a digital adder which avoids the above problem is disclosed in a technical paper entitled "High-Speed CMOS adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment" by Kershof et al, IEEE Journal of solid-state circuits, Vol. 24, No. 3, Jun. 1989, pages 570-575. In this paper, FIG. 5 shows a circuit diagram of a digital adder in which the signal path from the carry-in signal for the least significant bits, to the carry-out terminal from the most significant bits, goes through one input inverter and the channels of several transistors and one output inverter. A separate transistor channel is included for each pair of data bits being added. This adder circuit avoids the time delay through a serial string of logic gates by replacing it with a shorter time delay through a serial string of transistor channels.
Still another structure, in the prior art, of a digital adder which is a variation on the Kershof et al adder is disclosed in U.S. Pat. No. 5,025,409 by Goto issued Jun. 18, 1991. Various embodiments of the Goto adder are shown in his FIGS. 3 thru 9c; but, the gist of each of these embodiments is to provide a bypass circuit for the serial string of transistor channels. However, for each of the Goto embodiments, a signal path still exists from the carry-in terminal to the carry-out terminal which, in a certain worst case scenario, will have a large signal propagation delay.
For example, Goto's FIG. 3 embodiment includes three bypass circuits #1', #2', and #3'. In the case where each of those bypass circuits is active, the initial carry-in signal C.sub.0 travels through a first carry circuit #1', then through bypass circuit #1', then through bypass circuit #2', and then through a last carry circuit #(L+2).
At the same time, however, the carry-in signal C.sub.0 also travels through other circuits. Specifically, the carry-in signal C.sub.0 travels through all of the carry circuits #2-#m, then through bypass circuit #3', and then through carry circuits #1-#(m+2). Each of those circuits has an inherent capacitance associated with the channel of a transistor (labeled 1 in FIG. 4a), and the total capacitance from those transistors in all of the circuits #2-#m, #3', and #1-#(m+2) is coupled to the output terminal of circuit #1. Consequently, the propagation delay from circuit #1 to circuit #1' is slowed down.
A similar capacitive loading problem also exists for all of Goto's embodiments. For example, in the embodiment of FIG. 7B, the bypass path for the carry-in signal C.sub.i-1 goes through the channel of a bypass transistor (labeled 2) and through an inverter (not labeled) to form the carry-out signal C.sub.i+3. At the same time however, the carry-in signal C.sub.i-1 also goes through the channel of an extra transistor (labeled 1) to the input of an extra inverter (not labeled); and, the output from the channel of the bypass transistor 2 goes to the channel of another extra transistor (labeled 1). All of these extra components add capacitance to the bypass path, and that slows down the speed at which signals propagate along the bypass path.
Further, all of Goto's embodiments are incomplete in that they do not form any sum bits from the carry signals. To form those sum bits, EXCLUSIVE-OR gates need to be coupled to the channels of each of the transistors 1, and that adds even more capacitance to the bypass path. For example, in Goto's FIG. 7B embodiment, one EXCLUSIVE-OR gate would be added to the input of the leftmost transistor 1 and another EXCLUSIVE-OR gate would be added to the input of the rightmost transistor 1.
Accordingly, a primary object of the invention is to provide a digital adder circuit which overcomes the above described prior art problems and which operates faster than the prior art adders.